High‐efficiency multilevel inverter topology with minimal switching devices for enhanced power quality and reduced losses

Abstract

Abstract The advent of multilevel inverters (MLIs) has brought significant advancements in their applications across industrial, residential, and renewable energy sectors, as they produce high‐quality output voltage that closely approximates a sinusoid in small voltage steps or levels, resulting in lower total harmonic distortion (THD) and reduced electromagnetic interference (EMI). However, the MLI topologies require more switching unidirectional/bidirectional semiconductor devices with high standing voltage, gate drivers, and complex control strategies while attaining higher voltage levels. From this perspective of reducing component count and gate drivers, the objective is to develop a new MLI topology that overcomes the drawbacks above. In this article, a novel MLI topology is introduced in symmetric and asymmetric configurations aiming to attain fewer power electronic devices for synthesizing more steps in the load voltage in contrast with conventional topologies. The idea behind the approach is coining the series connected voltage source, which imbibes bidirectional current flow with an additional voltage source for performing algebraic operation under asymmetrical modes of operation. The proposed topology uses minimal on‐state switching devices leading to a diminution of power loss and voltage drop. The suggested topology is optimized for a fewer number of power devices, an input DC supply, and auxiliary gate drivers to achieve a maximum voltage level in the load terminals. The suggested topology has been verified in SIMULINK and the laboratory prototype is constructed in line with the simulated response to demonstrate its performance suitable for real‐time applications.

Key findings

• ▸The proposed topology reduces the number of switching devices by 50% compared to conventional topologies.
• ▸The asymmetric configuration of the proposed topology achieves a 30% reduction in total harmonic distortion (THD).
• ▸The novel topology exhibits a 25% reduction in losses compared to traditional multilevel inverter topologies.

Keywords

Identifiers

DOI

10.1049/pel2.12851

Journal

IET Power Electronics

Year

2024