Optimal peak‐efficiency control of the CMOS interleaved multi‐phase step‐down DC‐DC Converter with segmented power stage

Abstract

This study presents concept of the power‐efficiency optimisation of interleaved step‐down DC/DC converter with segmented power stages. Use of segmented power stage is based on continuous adjusting of the size of power switches, and is currently exclusively employed in the single‐phase topologies. The size control use accurate peak‐efficiency detection method. Employed iterative algorithm allows to equilibrate the dissipated dynamic and Joule powers in wide range of operating parameters such as output current, input/output voltages, temperature, switching frequency, or variation of the process. By the balancing of dynamic and Joule power losses, peak efficiency is achieved in low and middle output power range. This allows to increase the power efficiency by several per cent, when compared with the phase shedding approach. Moreover, use of the segmented switches enables to maintain all power stages active during light‐load operation. This allows to benefit from reduced AC input/output currents of the multi‐phase topology. This study describes the efficiency optimisation of interleaved power converters, technique of the peak‐efficiency detection, and shows comparison of results obtained by the presented peak‐efficiency tracking and phase shedding approach.

Key findings

• ▸Peak efficiency is achieved in the low and middle output power range by balancing dynamic and Joule power losses.
• ▸The use of segmented switches enables maintaining all power stages active during light-load operation, reducing AC input/output currents.
• ▸The proposed method increases power efficiency by several percent compared to the phase shedding approach.

Keywords

Identifiers

DOI

10.1049/iet-pel.2015.0814

Journal

IET Power Electronics

Year

2016